This invention relates to a semiconductor device, particularly, a technique effective when adapted to a semiconductor device having a trench-gate structure.
A power transistor has been used for various applications including a power amplifier circuit, power supply circuit, converter and power supply protective circuit. Since it treats high power, it is required to have high breakdown voltage and to permit high current.
In the case of MISFET (Metal Insulator Semiconductor Field Effect Transistor), high current can be attained easily by an expansion of a channel width. In order to avoid an increase in a chip area caused by expansion of a channel width, a mesh-gate structure is, for example, employed.
Gates are two-dimensionally arranged in the form of a lattice in the mesh-gate structure so that a channel width per unit chip area can be enlarged. A description of an FET having a mesh-gate structure can be found on pages 429 to 430 of “Semiconductor Handbook” published by Ohmsha Limited or U.S. Pat. No. 5,940,721.
For such a power FET, a planar structure has conventionally been employed because its fabrication process is simple and an oxide film which will be a gate insulating film can be formed easily. In the above-described U.S. Pat. No. 5,940,721 shown is an FET having a planar structure.
The FET having a planar structure is however accompanied with the drawbacks that when a gate is formed narrowly, the channel length becomes short and a short-channel effect appears because the channel length is determined depending on the gate length; or when a gate is formed narrowly, an allowable current decreases because the gate has additionally a function of wiring. It is therefore impossible to conduct miniaturization freely. With the foregoing in view, adoption of an FET having a trench-gate structure is considered because it can improve the integration degree of cells and in addition, reduce an on resistance.
The trench-gate structure is formed by disposing, via an insulating film, a conductive layer, which will serve as a gate, in a trench extended in the main surface of a semiconductor substrate and in this structure, the deeper portion and the outer surface portion of the main surface serve as a drain region and a source region, respectively and a semiconductor layer between the drain and source regions serves as a channel forming region. Such a structure is described, for example, in U.S. Pat. No. 5,918,114.
The present inventors developed a technique for introducing impurities into a source region or channel forming region of an MISFET having a trench-gate structure after the formation of a trench gate with a view to preventing a deterioration of a gate insulating film or a fluctuation in a threshold voltage owing to the impurities in the source region or channel forming region and have already applied for a patent as U.S. patent application Ser. No. 09/137,508.